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UPF Design Verification Engineer

Sicon Tech  |  posted over 4 years ago

FullTime | Staffing Agency | Austin, TX


Description:

Minimum Requirements:

- Bachelor of Science degree in Electrical or Computer Engineering with at least 5 years' experience or Master of Science degree in Electrical or Computer Engineering in Front End development. 

- 5+ years of experience in RTL Level Digital IC Design using System Verilog, Verilog and VHDL 
- 4+ years of experience in Strong ASIC and/or SoC Design
- 4+ years of experience with industry standard FE Development and Verification Tools and Methodologies 

The following skills would be an added advantage: 
- Experience with languages such as C and/or C++, SystemC, System Verilog*, OVM, Perl, Specman e, Shell scripting 
- Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS*, PrimeTime, Design Compiler, Jasper, 0in. UPF 
- Experience with low power design and power management

- A self-starter with the ability to assume leadership roles 
- Ability to work well in a diverse team environment 

Need more information? Submit your question to employer
Kam***@***.Com over 4 years ago

Hi There,

Greetings,

I hope you are doing great. I would like to know if this position is still open. If yes, we can refer some good candidates.

Kindly also share some more details such as place of work, payout , Benefits etc..

Regards,

Amit (Alex)

Dawn Gray almost 4 years ago

Is this still open? In order to attract the most viable candidates I need to know the following please: salary, benefits, relocation package. Most candidates want to know this information to help them with their decision of whether or not this is a good fit for them just as the client company wants the candidate to be a good fit for the success and growth of their business. Recruiters are in sort match makers, so we need as much information as possible from both parties so that it is a very successful uniting. Please elaborate.