UPF Design Verification Engineer

 posted over 4 years ago

Sicon Tech | FullTime | Austin, TX


Minimum Requirements:

- Bachelor of Science degree in Electrical or Computer Engineering with at least 5 years' experience or Master of Science degree in Electrical or Computer Engineering in Front End development. 

- 5+ years of experience in RTL Level Digital IC Design using System Verilog, Verilog and VHDL 
- 4+ years of experience in Strong ASIC and/or SoC Design
- 4+ years of experience with industry standard FE Development and Verification Tools and Methodologies 

The following skills would be an added advantage: 
- Experience with languages such as C and/or C++, SystemC, System Verilog*, OVM, Perl, Specman e, Shell scripting 
- Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS*, PrimeTime, Design Compiler, Jasper, 0in. UPF 
- Experience with low power design and power management

- A self-starter with the ability to assume leadership roles 
- Ability to work well in a diverse team environment