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Analog Mixed Signal Modelling
- Candidate should have 3-8 years’ experience in Mixed Signal or Analog Verification
- Candidate should have hands on experience in developing Analog models using Verilog-A/Verilog-AMS
- Candidate should have hands on experience in developing Analog/Digital Real models using Verilog/VHDL
- Experience on modeling Power Management/PLL/ADC, etc is required
- Experience in Cadence flow is required
- Experience in Mixed signal verification using System Verilog & UVM is a plus.
- Candidate should have good communication skills.
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